1. Field of the Invention
The present invention relates to a semiconductor device with a bus connection circuit adapted to make communication with an external device, and a method of making bus connection to the external device from the semiconductor device.
2. Background Art
FIG. 1 of the accompanying drawings shows a circuit configuration of two conventional semiconductor devices (LSIs: large-scale integrations) 1 and 2 with the same bus connection circuit. The bus connection circuit is compatible with what is called an I2C bus. Each of the LSIs 1 and 2 includes an MCU (micro control unit) 11, an I2C circuit 12, and two IO buffer circuits 13 and 14 that form in combination the bus connection circuit. Each of the LSIs 1 and 2 also includes two connecting terminals, namely a serial clock terminal SCL and a serial data terminal SDA. The MCU 11 is an arithmetic processor for controlling the entire LSI, and operates according to a program stored in an internal ROM (not shown) and/or RAM (not shown). The I2C circuit 12 is a logic circuit, and it is controlled by the MCU 11 to control an I2C bus function. More specifically, the I2C circuit 12 supplies output enable signals OE separately to the IC buffer circuits 13 and 14, and receives input signals A separately from the IO buffer circuits 13 and 14. Each of the IO buffer circuits 13 and 14 is an input and output buffer having an open drain function. The IO buffer circuit 13 is provided for input and output of a clock signal, and is connected to the serial clock terminal SCL. The IO buffer circuit 14 is designed for input and output of a data signal, and is connected to the serial data terminal SDA.
The respective serial clock terminals SCL of the LSIs 1 and 2 are connected to each other through a bus line B1. The respective serial data terminals SDA of the LSIs 1 and 2 are connected to each other through another bus line B2. A voltage VDD is applied through a pull-up resistor R1 to the bus line B1. The voltage VDD is also applied through another pull-up resistor R2 to the bus line B2.
As shown in FIG. 2 of the accompanying drawings, each of the IO buffer circuits 13 and 14 has an output buffer 15 with an enable terminal, and an input buffer 16. The output buffer 15 operates in response to an output enable signal OE supplied to an enable terminal 15a. The output buffer 15 of the IO buffer circuit 13 supplies a clock signal to the serial clock terminal SCL when the output enable signal OE is at a low level representing a logic 0. The output buffer 15 of the IO buffer circuit 14 supplies a data signal to the serial data terminal SDA when the output enable signal OE is at a low level representing a logic 0. The output buffer 15 is at high impedance when the output enable signal OE is at a high level representing a logic 1. The input buffer 16 of the IO buffer circuit 13 supplies a signal of the serial clock terminal SCL as the input signal A to the I2C circuit 12. The input buffer 16 of the IO buffer circuit 14 supplies a signal of the serial data terminal SDA as the input signal A to the I2C circuit 12.
FIG. 3 of the accompanying drawings shows a truth table relating to input and output signals of each of the IO buffer circuits 13 and 14. In this truth table, OE represents the logic value of the output enable signal OE, A represents the logic value of the received signal A, and Y represents the logic value at the terminal SCL or SDA. Hiz represents the state of high impedance, and X represents a state when a logic value is neither 0 nor 1.
FIG. 4 of the accompanying drawings shows a timing chart for the signals OE, A and Y when the right of using the I2C bus between the LSIs 1 and 2 is acquired. In the master LSI 1, the signal Y of the clock terminal SCL makes transition to a logic 0 when the output enable signal OE of the IO buffer circuit 13 becomes a logic 0. When the output enable signal OE of the IO buffer circuit 13 changes to a logic 1, the output buffer 15 is brought to a high impedance state, so that the signal Y is caused by the pull-up resistor R1 to make transition to a logic 1. When the output enable signal OE of the IO buffer circuit 14 becomes a logic 0, the signal Y of the data terminal SDA makes transition to a logic 0. Conditions for starting communications between the two devices 1 and 2 are met if the data terminal SDA becomes a logic 0 while the clock terminal SCL is at a logic 1. Thus, acquisition of the right of using the I2C bus is completed.
Data of the data terminal SDA is valid while the clock terminal SCL is at a logic 1. Data can be changed while the clock terminal SCL is at a logic 0. In FIG. 4, Dout0 and Dout1 that are parts of the signal Y of the data terminal SDA show data to be transferred from the master LSI 1 to the slave LSI 2. Din0 and Din1 that are parts of the signal Y of the data terminal SDA in the slave LSI 2 show the received data.
A plurality of LSIs may be connected to a bus line outside an LSI. Accordingly, the configuration of an LSI with the above-described conventional bus connection circuit always requires a pull-up resistor of a low resistance value so that a sufficient current can be supplied to a bus connection circuit of each of the LSIs. This results in a larger number of external parts, and an increased value of a current flowing through the pull-up resistor.
A countermeasure technique thereto is disclosed, for example, in Japanese Patent Application Publication (kokai) No. 2-138612. A pull-up resistor is incorporated into an LSI to reduce the number of external parts, and the pull-up resistor is not connected to a bus line. However, communication through a bus line is not limited to that between those LSIs which have the pull-up resistors incorporated without connecting the pull-up resistors to the bus line. If an LSI with a pull-up resistor incorporated therein is mounted on an existing system equipped with another ordinary LSI and a bus line, communication between these two LSIs through a bus line should be established by using a pull-up resistor provided on the bus line of the existing system. Accordingly, the mounted LSI only with a pull-up resistor incorporated therein cannot perform desirable communication behavior through the system bus line although the mounted LSI looks a part of the existing system.